1. Field of the Invention
The present invention relates to a master slice type semiconductor integrated circuit capable of appropriately selecting a load drive capacity of an output signal.
2. Description of the Related Art
Basic logic gates are formed at a master level, and a wiring pattern for connecting these basic logic gates is formed in a subsequent step to obtain a basic logic gate circuit or an input/output circuit. The master slice scheme has an advantage in that various types of ICs in small quantities can be manufactured within a short period of time.
FIG. 1 is a view showing chip layout of a conventional master slice type semiconductor integrated circuit. An internal logic block 22 is formed at the center of a chip body 21, and I/O cells 23 constituted by input and output buffers and the like (not shown) are arranged in the peripheral portion at a predetermined pitch. A pad 24 is arranged for each I/O cell in a one-to-one correspondence. The pads 24 are arranged at the same pitch as the I/O cells. After the step of the master level, a wiring pattern is formed to connect the components within the internal logic block 22, between the internal logic block 22 and the I/O cells 23, and between the I/O cells 23 and the corresponding pads 24. Each pad 24 serves as an input or output pad, or an input/output pad. After the wiring pattern on the chip body is formed, each pad is wire-bonded to a corresponding pin of an IC.
The electrical characteristics such as a load drive capacity as well as areas of the respective I/O cells 23 are equal to each other in favor of easy cell design. For this reason, when a large load capacitor is driven, the drive capacity may be insufficient when only one I/O cell is used. In a conventional arrangement, as shown in FIG. 2, in order to increase the load drive capacity, output buffers in a plurality of I/O cells are connected in parallel with each other, as disclosed in Japanese Patent Disclosure (Kokai) No. 60-169150. Referring to FIG. 2, reference numerals 23a to 23e denote I/O cells each including an input buffer 25 and an output buffer 26; and 24a to 24e, pads formed in one-to-one correspondence with the I/O cells 23a to 23e. The pads 24a, 24c, and 24d are connected to only the input buffers 25 in the I/O cells 23a, 23c, and 23d, respectively. In this case, these pads are used as the input pads. The pad 24b is connected in parallel with the output buffers 26 in the two I/O cells 23a and 23b. The pad 24b is used as an output pad having a load drive capacity twice an I/O cell. The pad 24e is connected in parallel with output buffers 26 in the three I/O cells 23c, 23d, and 23e. The pad 24e is used as an output pad having a load drive capacity three times an I/O cell.
As described above, output buffers in a plurality of I/O cells are connected in parallel with each other at the time of formation of a wiring pattern. Therefore, the load drive capacity can be arbitrarily selected without changing the size of the chip body.
In the conventional IC shown in FIG. 2, when a pad pitch must be changed due to demand for a multi-pin IC, I/O cells each having a new shape must be designed again, thus wasting time and cost.